Mpc850 Hardware Interface - Freescale Semiconductor MPC850 User Manual

Overview of Major Components
The MPC850 has several sources of input to the reset logic:
• Power-on reset
• External hard reset
• Internal hard reset
— Loss of lock
— Software watchdog reset
— Checkstop reset
— Debug port hard reset
• JTAG reset
• External soft reset
• Internal soft reset (debug port soft reset)
All of these reset sources are fed into the reset controller and, depending on the source of
the reset, different actions are taken. The reset status register reflects the last source to cause
a reset.

1.2.3 MPC850 Hardware Interface

The MPC850 bus is a synchronous, burstable bus that can support multiple masters. Signals
driven on this bus are required to make the setup and hold time relative to the bus clock's
rising edge. The MPC850 architecture supports byte, half-word, and word operands
allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles
controlled by the size outputs (TSIZ0, TSIZ1). Access to 16- and 8-bit ports is done for
slaves controlled by the memory controller.
The MPC850 bus interface features are listed as follows:
• 26-bit address bus with transfer size indication
• 32-bit data bus
• Dynamic bus sizing to 32-, 16-, or 8-bit ports accessed through the memory
controller
• TTL-compatible interface
• Bus arbitration supported optionally by internal or external logic
• Bus arbitration logic on-chip supports an external master with programmable
priority
• Compatible with PowerPC architecture
• Easy to interface to slave devices
• Bus is synchronous (all signals are referenced to rising edge of bus clock)
• Contains support for data parity
The PCMCIA host adapter module provides all control logic for a PCMCIA socket
interface, and requires only additional external analog power switching logic and buffering.
MPC850 Family User's Manual