Pcmcia Base Registers 0–7 (Pbr0–Pbr7); Pcmcia Option Register 0–7 (Por0–Por7) - Freescale Semiconductor MPC850 User Manual

Programming Model
Table 16-11 describes PGCRB fields.
Bits Name
0–7 CBIREQLVL Card B IREQ_B interrupt level. Only one bit of this field should be set at any time.
8–15 CBSCHLVL Card B STSCHG_B interrupt level. Only one CASCHLVLB bit should be set at any time.
16–17 CBDREQ Card B DREQ. Defines internal DMA request for the on-chip DMA controller (CBDREQ
controls DMA channel 1).
0x Disable internal DMA request from slot B.
10 Enable IOIS16_B as internal DMA request for slot B.
11 Enable SPKR_B as internal DMA request for slot B.
18–23 — Reserved, should be cleared.
24 CBOE Card B output enable. CBOE is reflected on OP2 used to three-state the external buffers
when the card's power is activated.
25 CBRESET Card B reset. CBRESET is reflected on OP3 used to reset card B.
26–31 — Reserved, should be cleared.
16.4.5 PCMCIA Base Registers 0–7 (PBR0–PBR7)
Setting a bit in the PBR, shown in Figure 16-5, enables the corresponding interrupt.
Bit 0 1 2
Field
Reset
R/W
Addr (IMMR & 0xFFFF0000) + 0x080 (PBR0); 0x088 (PBR1); 0x090 (PBR2); 0x098 (PBR3); 0x0A0 (PBR4); 0x0A8
Table 16-12 describes the PBR.
Bits Name
0–31 PBA PCMCIA base address. Compared to the address on the address bus to determine if a PCMCIA
window is being accessed by an internal bus master. PBA is used in conjunction with POR[BSIZE].
16.4.6 PCMCIA Option Register 0–7 (POR0–POR7)
The POR, shown in Figure 16-8, as the manipulation of timing, provides the address mask
for the bank size, and defines the region, slot, write protection, and validation.
Table 16-11. PGCRB Field Descriptions
3 4 5
(PBR5); 0x0B0 (PBR6); 0x0B8 (PBR7)
Figure 16-7. PCMCIA Base Register (PBR)
Table 16-12. PBR Field Descriptions
MPC850 Family User's Manual
Description
...
PBA
—
R/W
Description
31