Single-Buffer Mode On Idma1—A Special Case - Freescale Semiconductor MPC850 User Manual

IDMA Emulation
T3
CLKOUT
Address
TS
R/W
Data
TA
SDACK
Figure 19-12. SDACK Timing Diagram: Single-Address
19.3.9 Single-Buffer Mode on IDMA1—A Special Case
For single-buffer transfers from a peripheral to memory of up to 64 bytes per request,
IDMA1 offers a reduced-latency solution using single-address bursts. The memory
destination address, the buffer length (byte count), and the channel mode register are stored
directly in the IDMA parameter RAM instead of in a formal BD. Table 19-9 shows the
single-buffer mode IDMA1 parameter RAM map.
Table 19-9. Single-Buffer Mode IDMA1 Parameter RAM Map
1
Offset Name Width
BAPR
0x00 Word
BCR
0x04 Word
DCMR
0x08 Word
0x0C–0x3F —
Note: Parameters should not be modified while DMA is active.
1
From IDMA1 base = IMMR + 0x3CC0
Single-buffer mode is selected by setting RCCR[EIE], the CPM external interrupt enable
bit; see Section 18.5.1, "RISC Controller Configuration Register (RCCR)." Note that the
CPM external interrupt always refers to a special request to the CPM, not to the core.
T1 T3 T1
T
DELAY
Peripheral Read, Internally-Generated TA
Buffer pointer. Contains the destination buffer memory address. BAPR should be
burst-aligned. It is automatically incremented by 16 bytes after each burst.
Byte count register. Contains the buffer length in bytes. BCR is decremented by 16
after each burst. BCR must be a multiple of 16. The IDMA channel will terminate the
block transfer when BCR reaches zero.
DMA channel mode register.
— Reserved.
MPC850 Family User's Manual
T3 T1 T3 T1
Description
T3 T1 T3
T
HOLD