Machine A Mode Register/Machine B Mode Registers (Mxmr) - Freescale Semiconductor MPC850 User Manual

Register Descriptions
Bit 0 1 2
Field
Reset
R/W
Addr
Bit 16 17 18
Field G0CLx
Reset 000
R/W
Addr
Figure 15-10. Machine A Mode Register/Machine B Mode Registers (MxMR)
Table 15-6 describes bits for MAMR/MBMR.
Bits Name
Periodic timer x period. Affects periodic timer x and determines the timer period service rate
0–7 PTx
according to the following equation, which determines value for UPMx to refresh memory:
NCS is an integer between 1 and 8 that represents the number of enabled chip selects that are
serviced by this UPM. SCCR[DFBRG] is defined in Section 14.6.1, "System Clock and Reset
Control Register (SCCR)." For example, for DRAM to maintain data integrity, an access or
refresh must occur every 15.6 µs. Given a 25-MHz system clock with the required service rate
of 15.6 µs, a periodic timer prescaler = 32, and DFBRG = 0, PTx = (25 × 15.6) / (2
= 12.
8 PTxE Periodic timer x enable. Allows the periodic timer x to request service.
0 Periodic timer x is disabled.
1 Periodic timer x is enabled.
Address multiplex size x. When internal address multiplexing is used, this field specifies how
9–11 AMx
the address on the external bus is multiplexed, when enabled (see Table 15-18). The SAM bit
enables address multiplexing in the first clock cycle. The AMx field of the RAM array entry
enables address multiplexing in subsequent clock cycles. (see Table 15-19).
12 — Reserved, should be cleared.
3 4 5
PTx
0000_0000_0000_0000
(IMMR & FFFF0000) + 0x170
19 20 21
GPLx4DIS RLFx
1 0000
(IMMR & FFFF0000) + 0x172
Table 15-6. MxMR Field Descriptions
System Clock (MHz) Service Duration (µs)
PTx = -------------------------------------------------------------------------------------------------------------------- -
2 ×
SCCR DFBRG [
2
MPC850 Family User's Manual
6 7 8 9 10
PTxE AMx
R/W
22 23 24 25 26
WLFx
0000
R/W
Description
×
]
Prescaler (PTP) NCS
× ×
11 12 13 14 15
— DSx —
27 28 29 30 31
TLFx
0000
2×0
× 32× 1)