Memory Command Register (Mcr) - Freescale Semiconductor MPC850 User Manual

Table 15-6. MxMR Field Descriptions (Continued)
Bits Name
13–14 DSx Disable timer period. Guarantees a minimum time between accesses to the same memory
bank if it is controlled by the UPMx. This function can be used to guarantee a minimum RAS
precharge time. The TODT bit in the RAM array turns on the disable timer and, when expired,
the UPMx allows the machine access to issue a memory pattern to the same region. An access
attempted before the timer expires (as signalled by TS assertion) has wait states inserted
before the UPM pattern runs. Accesses to other chip-selects serviced by this UPM are
unaffected by this timer. The maximum disable period is four clock cycles. If more than 4 cycles
are required, they must be added explicitly in the UPM RAM words.
00 1-cycle disable period
01 2-cycle disable period
10 3-cycle disable period
11 4-cycle disable period
15 — Reserved, should be cleared.
G0CLx[0–2] General line 0 control x. Selects the address line output to the internal GPL0 signal in the
16–18
special case where the functionality is enabled in the G0L and G0H bits of the UPM RAM word.
000 = A12
001 = A11
010 = A10
011 = A9
19 GPLx4DIS GPLx4 output line disable. Determines whether UPWAITx/GPL_x4 behaves as the GPL4
output controlled the UPM RAM word, or an input signal used to dynamically insert wait states
into UPM patterns.
0 = UPWAITx/GPL_x4 is defined as GPL_x4.
1 = UPWAIT
Read loop field x. Specifies (in binary) the number of times a loop defined in the UPMx RAM
20–23 RLFx
word is executed for a burst read or single-beat read cycle. (0001 = 1 time, 0010 = 2 times, ...,
1111 = 15 times; note that 0000 = 16 times.)
Write loop field x. Specifies the number of times a loop defined in the UPMx RAM word is
24–27 WLFx
executed for a burst- or single-beat write cycle. (0001 = 1 time, 0010 = 2 times, ..., 1111 = 15
times; note that 0000 = 16 times.)
Timer loop field x. Specifies the number of times a loop defined in the UPMx RAM word is
28–31 TLFx
executed for a periodic timer service. (0001 = 1 time, 0010 = 2 times, ..., 1111 = 15 times; note
that 0000 = 16 times.)

15.4.5 Memory Command Register (MCR)

The memory command register (MCR) is used during UPM initialization to read and write
the contents of the UPM RAM. It also allows commands to be issued that stimulate UPM
routine execution. This capability lets the CPU perform special memory operations in
addition to standard read/write and periodic timer service operations. An example of this is
software execution of a special UPM pattern to initialize SDRAM.
/GPL_x4 is defined as UPWAITx.
X
Chapter 15. Memory Controller
Description
100 = A8
101 = A7
110 = A6
111 = A5
Register Descriptions