Timer Gating (Timers 1 And 2 Only); Cascaded Mode - Freescale Semiconductor MPC850 User Manual

17.2.2.4 Timer Gating (Timers 1 and 2 only)

Timers 1 and 2 can be gated or restarted by an external gate signal—TGATE1. Normal gate
mode enables the count on a falling edge of TGATE1 and disables the count on the rising
edge of TGATE1. This allows the timer to count conditionally, depending on the state of
TGATE1.
Restart gate mode is like normal gate mode, but also resets the counter on the falling edge
of TGATE1. The restart gate mode can be used for pulse interval measurement and bus
monitoring:
• Pulse measurement—The restart gate mode can measure a low pulse on TGATE1.
The rising edge of TGATE1 completes the measurement. If TGATE1 is externally
connected to TINx, it causes the timer to capture the count value and generate a
rising-edge interrupt.
• Bus monitoring—The restart gate mode can detect a signal that is abnormally stuck
low. The bus signal should be connected to TGATE1. The timer count is reset on the
falling edge of the bus signal and if the bus signal does not go high again within the
number of user-defined clocks, an interrupt can be generated.
The gate function is enabled in the TMR; the gate operating mode is selected in the TGCR.
Note that TGATE1 is internally synchronized to the system clock. However, if TGATE1
meets the asynchronous input setup time, the counter begins counting after one system
clock when the input clock source (TMRx[ICLK]) is internal.

17.2.2.5 Cascaded Mode

Timer 1 can be internally cascaded to timer 2 and timer 3 can be internally cascaded to timer
4 to form 32-bit timers. The TGCR is used to put the timers into cascaded mode, as shown
in Figure 17-4.
TRR, TCR, TCN connected to D[0–15]
TRR, TCR, TCN connected to D[0–15]
Figure 17-4. Timer Cascaded Mode Block Diagram
If TGCR[CASx] is set, the two corresponding timers function as a 32-bit timer with a 32-bit
TRR, TCR, and TCN. In this case, the mode registers TMR1 and TMR3 are ignored and
TMR2 and TMR4 are used to define the mode. Similarly, the capture is controlled by TIN2
or TIN4, and interrupts are generated by TER2 or TER4. In cascaded mode, the cascaded
TRR, TCR, and TCN should always be accessed with 32-bit bus cycles.
Timer 1
Capture
Timer 3
Capture
Chapter 17. Communications Processor Module and CPM Timer
CPM General-Purpose Timers
Timer 2
TRR, TCR, TCN connected to D[16–31]
Timer 4
TRR, TCR, TCN connected to D[16–31]
Clock
Clock