Scc Bisync Programming Example - Freescale Semiconductor MPC850 User Manual

Alternatively, after an SOH is received, a
exclude SOH from BCS accumulation and reset the BCS. Notice that PSMR[RBCS] is not
needed because the controller automatically excludes SYNCs and leading DLEs.
After the type of block is recognized, SCCE[RCH] should be masked. The core does not
interrupt data reception until the end of the current block, which is indicated by the
reception of a control character matching the one in the receive control character table.
Using Table 26-15, the control character table should be set to recognize the end of the
block.
After ETX, a BCS is expected; then the buffer should be closed. Hunt mode should be
entered when a line turnaround occurs. ENQ characters are used to stop sending a block
and to designate the end of the block for a receiver, but no CRC is expected. After control
character reception, set SCCM[RCH] to reenable interrupts for each byte of data received.

26.17 SCC BISYNC Programming Example

This BISYNC controller initialization example for SCC2 uses an external clock. The
controller is configured with RTS2, CTS2, and CD2 active. Both the receiver and
transmitter use CLK3.
1. Configure the port A pins to enable TXD2 and RXD2. Write PAPAR[12,13] and
PAODR[12,13] with ones and PADIR[12,13] with zeros.
2. Configure the port C pins to enable RTS2, CTS2, and CD2. Set PCSO[8,9] and
PCPAR[14]; clear PCPAR[8,9] and PCDIR[8,9,14].
3. Configure port A to enable CLK3. Set PAPAR[5] and clear PADIR[5].
4. Connect CLK3 to SCC2 using the serial interface. Set SICR[R2CS, T2CS] to 0b110.
5. Connect the SCC2 to the NMSI and clear SICR[SC2].
6. Initialize the SDMA configuration register (SDCR).
7. Assuming one RxBD at the beginning of dual-port RAM followed by one TxBD,
write RBASE with 0x0000 and TBASE with 0x0008.
8. Write 0x0041 to CPCR to execute the
This command updates RBPTR and TBPTR of the serial channel with the new
values of RBASE and TBASE.
RESET BCS CALCULATION
Table 26-15. Control Characters
Control Characters
ETX
ITB
ETB
ENQ
Next entry
INIT RX AND TX PARAMS
Chapter 26. SCC BISYNC Mode
SCC BISYNC Programming Example
should be issued to
E B H
0 1 1
0 1 0
0 1 1
0 0 0
0 X X
command for SCC2.