Cache Initialization After Reset; Debug Support - Freescale Semiconductor MPC850 User Manual

If a memory region is marked caching-allowed, the MPC850 assumes that it is the single
master in the system to that region. If a caching-allowed lwarx or stwcx. access misses in
the data cache, the transaction on the internal and external buses do not have a reservation.
If the memory region is marked caching-inhibited or the cache is locked, and the access
misses, then the lwarx instruction appears on the bus as a single-beat load with the
reservation.
lwarx and stwcx. accesses to write-through memory regions do not generate DSI
exceptions. The MPC850's data cache treats all stwcx. operations as write-through
independent of the memory/cache access attributes. When the write-through operation
completes successfully on the external bus, then the data cache entry is updated (assuming
it hits), and CR0[EQ] is modified to reflect the success of the operation. If the reservation
is not intact, the stwcx. cancels the external bus transaction, and the cache block is not
altered.

7.7 Cache Initialization after Reset

At power-on and hard reset, both caches are disabled. Although disabled, the cache state is
preserved to enable the user to investigate the exact state of the cache prior to the event that
caused the reset. To ensure proper operation after reset, initialize the instruction cache by
performing the following:
1. Write the unlock all command (IC_CST[CMD] = 0b101) to the IC_CST register.
2. Write the invalidate all command (IC_CST[CMD] = 0b110) to the IC_CST register.
3. Write the cache enable command (IC_CST[CMD] = 0b001) to the IC_CST register.
Similarly, to ensure proper operation after reset, initialize the data cache by performing the
following:
1. Write the unlock all command (DC_CST[CMD] = 0b1010) to the DC_CST register.
2. Write the invalidate all command (DC_CST[CMD] = 0b1100) to the DC_CST
register.
3. Write the cache enable command (DC_CST[CMD] = 0b0010) to the DC_CST
register.
After the caches are initialized, all the cache blocks are invalidated, and the LRU bits point
to way 0 of each set.

7.8 Debug Support

The MPC850 can be debugged either in debug mode or by a software monitor debugger. In
both cases the core of the MPC850 asserts the internal freeze signal. See Chapter 44,
"System Development and Debugging," for a detailed description of the MPC850 debug
support.
Chapter 7. Instruction and Data Caches
Cache Initialization after Reset