Entering Debug Mode - Freescale Semiconductor MPC850 User Manual

mode is enabled as described in this section, debug mode can be entered by the methods
described in Section 44.3.1.2, "Entering Debug Mode."

44.3.1.2 Entering Debug Mode

By appropriately programming the development port during reset, debug mode can be
entered immediately out of reset, thus allowing the user to debug a ROM-less system. If
DSCK is asserted throughout SRESET assertion and then past SRESET negation, the
processor takes a breakpoint exception and goes directly to debug mode instead of fetching
the reset vector.
To avoid entering debug mode after reset, DSCK must be negated no later than seven clock
cycles after SRESET negates, allowing the processor to jump to the reset vector and begin
normal execution. If debug mode is entered immediately after reset, as shown in
Figure 44-7, ICR[DPI] is set.
The user can enable events that can initiate debug mode and determine which events require
regular interrupt handling.
The following events can cause the core to enter debug mode. Each event results in debug
mode entry if debug mode is enabled and the corresponding enable bit is set in the DER.
The reset values of the enable bits allow use of the debug mode features without
programming the DER in most cases. See Table 44-25.
• System reset, as a result of the assertion of SRESET, as described in Section 6.1.2.1,
"System Reset Interrupt (0x00100)."
• Checkstop, as described in Table 44-9.
• Machine check interrupt.
• Implementation-specific ITLB miss.
• Implementation-specific ITLB error.
• Implementation-specific DTLB miss.
• Implementation-specific DTLB error.
• External interrupt, recognized when MSR[EE] = 1.
• Alignment exception.
• Program exception.
• Floating-point unavailable exception.
• Decrementer interrupt, recognized when MSR[EE] = 1.
• System call exception.
• Trace, asserted when in single or branch trace mode, as described in
Section 6.1.2.10, "Trace Exception (0x00D00)."
• Implementation-dependent software emulation exception.
Chapter 44. System Development and Debugging
Development System Interface