Updating Code And Memory Region Attributes; Data Cache Operation - Freescale Semiconductor MPC850 User Manual

Data Cache Operation

7.5.5 Updating Code and Memory Region Attributes

The instruction cache does not perform snooping, so if a processor modifies a memory
location that may be contained in the instruction cache, software must ensure that such
memory updates are visible to the instruction fetching mechanism. Also, whenever the
memory/cache attributes of any memory region are changed, it is critical that the cache
contents reflect the new attributes. Therefore, when updating code or changing memory
region attributes (in the MMU) the user must perform the following steps:
1. Update code/change memory region attributes
2. Execute a sync instruction to ensure the update/change operation finished
3. Unlock all locked cache blocks containing code that was updated
4. Invalidate all cache blocks containing code that was updated
5. Execute an isync instruction
7.6 Data Cache Operation
When the data MMU is enabled (MSR[DR] = 1), the data cache operates as defined by the
memory/cache access attributes. When the data MMU is disabled (MSR[DR] = 0), the data
cache operates as defined by the default data memory access attributes. The default state of
the write-through/write-back attribute is determined by MD_CTR[WTDEF]; the
caching-inhibited/caching-allowed attribute is determined by MD_CTR[CIDEF]; and the
entire memory space defaults to the guarded attribute. See Chapter 8, "Memory
Management Unit," for more information.
A data cache access begins with a load or store request from the load/store unit (LSU) in
the core. The data cache has a 32-bit data path to and from the load/store unit, allowing for
a 4-byte transfer per cycle. As shown in Figure 7-2, bits 23–27 of the data address provide
the index to select a set (0–31) within the data cache array. The tags from both ways of the
set are compared against bits 0–22 of the data address. If a match is found and the matched
entry is valid, then it is a cache hit. If neither tag matches or the matched tag is not valid, it
is a cache miss.
The data cache operates in both write-through and write-back modes as programmed by the
memory/cache access attributes. These modes affect store hit and store miss behavior of the
data cache. Load hits and load misses behave the same regardless of the
write-through/write-back mode. If two logical blocks map to the same physical block, it is
considered a programming error for them to specify different cache write policies.
Each data cache block contains two state bits that implement a three-state
(modified-valid/unmodified-valid/invalid) protocol. The MPC850 does not support
snooping of the data cache. All memory is considered to have memory coherency not
required attributes. Therefore, software must maintain data cache coherency. The MPC850
does not provide support for snooping external bus activity. All coherency between the
internal caches and external agents (memory or I/O devices) must be controlled by
MPC850 Family User's Manual