Power-Down Mode; Software Initiation Of Power-Down Mode, With Automatic Wake-Up - Freescale Semiconductor MPC850 User Manual

Power Control (Low-Power Modes)
Deep-sleep mode is selected if PLPRCR[LPM]=11 and PLPRCR[TEXPS]=1. Note also
that PLPRCR[TMIST] should be cleared before entering deep-sleep mode; for more
information, see Section 14.5.8, "TMIST: Facilitating Nesting of SIU Timer Interrupts."
Note that the RTC, PIT, TB, and DEC operate in deep-sleep mode only if their timing
reference is OSCM. In all other aspects, the behavior of deep-sleep mode is identical to that
of sleep mode.

14.5.7 Power-Down Mode

Power-down mode describes the condition where a power source is applied to KAPWR, but
the power source for VDDH, VDDL, and VDDSYN has been shut down. The behavior in
this mode is similar to deep-sleep mode, in that the SPLL is shut down and only the
real-time clock (RTC), periodic interrupt timer (PIT), timebase (TB), and decrementer
(DEC) are active. The RTC, PIT, TB, and DEC operate in power-down mode only if their
timing reference is OSCM.
In normal operation, KAPWR should be greater than or equal to approximately
(VDDH - 0.4) V. In power-down mode, KAPWR should be greater than or equal to 2.0 V.
If power-down mode is used, connect KAPWR to both VDDH and the back-up battery
through diodes. To prevent battery current from being drawn when VDDH is active, the
back-up battery voltage should be greater than 2.4 V but less than (VDDH - 0.4) V. If,
however, power-down mode is not used, tie KAPWR directly to VDDH.
Exiting from power-down mode requires a full hardware reset. Note that if it is required that
the PIT, TB, DEC, and SPLL registers and settings not change during power-down mode
and the subsequent reset, then PORESET should be pulled high throughout power-down
mode and HRESET should be used for the reset during wake-up. Otherwise, PORESET can
be used for this reset source. After initial power-up, PORESET assertion does not affect the
RTC registers.
To maintain stability of the crystal oscillator, switchover between the main power supply
and KAPWR supply should be done smoothly. The maximum power supply rise time seen
at the KAPWR pin should be less than 1.7 V/ms for a 32-kHz input frequency. This can be
done by connecting a capacitor from KAPWR to ground.
Power-down mode can be used for:
• A software-initiated controlled shutdown, with optional automatic wakeup,
• Maintaining integrity of the real-time clock (RTC) during a power failure.
14.5.7.1 Software Initiation of Power-Down Mode, with Automatic
Wake-up
Power-down mode can be initiated in software if the external TEXP signal is used to control
the power supply for VDDH, VDDL, and VDDSYN. If software clears TEXPS, the TEXP
MPC850 Family User's Manual