Development System Interface - Freescale Semiconductor MPC850 User Manual

7. Enable a trap on every watchpoint or every N watchpoints.
Option: Enable trap on every load/store watchpoint in LCTRL2[SLWxEN] or on
every N watchpoints in COUNTx. (Set CNTV to n and select the load/store
watchpoint in CNTC).
8. Select whether breakpoints are maskable or nonmaskable in
LCTRL2[BRKNOMSK].
9. Optionally select whether a load/store trap causes the debug mode to be entered in
DER[LBRKE].

44.3 Development System Interface

It is often useful to debug a target system without making changes. However, sometimes it
is impossible to add load to the lines connected to the existing system without disrupting
its operation. The development system interface of the core enables debug of a target
system with minimal cost and intrusiveness.
The development system interface of the core uses the development port, which is a
dedicated serial port and, therefore, does not need any of the regular system interfaces.
The development port is a relatively inexpensive interface that allows a development
system to operate in a lower frequency than the core's frequency and controls system
activity when the core is in debug mode. It is also possible to debug the core using monitor
debugger software, described in Section 44.4, "Software Monitor Debugger Support."
In debug mode the core fetches all instructions from the development port; data can be read
from the development port and written to the development port. This allows memory and
registers to be read and modified by a development tool (emulator) connected to the
development port. For protection, two possible working modes are defined—debug mode
enable and debug mode disable, described in Section 44.3.1.1, "Debug Mode Enable vs.
Debug Mode Disable," are selected only during reset.
The user can work in debug mode directly out of reset or the core can be programmed to
enter debug mode as a result of a predefined sequence of events. These events can be any
interrupt or exception in the core system, including the internal breakpoints, in combination
with two levels of development port requests generated externally. Each of these can be
programmed to be treated as a regular interrupt that causes the machine to branch to its
interrupt vector or as a special interrupt that causes debug mode entry. In debug mode, the
rfi instruction returns the machine to its regular work mode. Figure 44-5 shows the
relationship between debug mode logic and the rest of the core.
Chapter 44. System Development and Debugging
Development System Interface