Implementing The Precise Exception Model - Freescale Semiconductor MPC850 User Manual

Exceptions
Execution resumes from the following offsets from the base indicated by the MSR[IP]:
• 0x01D00–For an instruction breakpoint match
• 0x01C00–For a data breakpoint match
• 0x01E00–For a development port maskable request or a peripheral breakpoint
• 0x01F00–For a development port nonmaskable request

6.1.4 Implementing the Precise Exception Model

Because instructions execute in parallel they may execute out of order. To ensure that
out-of-order execution does not affect data integrity, hardware ensures a precise exception
model. As instructions are dispatched in-order to the execution units, they are assigned
sequential positions in the six-entry completion queue, a FIFO buffer maintains program
order. The completion queue is shown in Figure 3-2.
When an exception condition is encountered, previous instructions in the completion queue
are allowed to complete and be retired from the completion queue. If one of these
instructions generates another exception, that exception is handled first. Subsequent
instructions, and any results associated with them, are flushed from the processor before
instruction processing resumes at the appropriate exception vector. Before control passes
to the exception handler, machine state is saved in SRR0 and SRR1.
After an exception handler executes, the machine state of the interrupted process is
restored, typically by executing the rfi instruction, which writes bits from SRR1 to the
MSR, SRR0 contains the instruction address at which fetching should resume. To correctly
restore the architectural state, the CQ must record the value of the destination before the
instruction is executed. The destination of a store instruction, however, is in memory and it
is not practical from a performance standpoint to always read memory before writing it.
Therefore, stores issue immediately to store buffers but do not update memory until all
previous instructions have finished executing without exception or until the store
instruction reaches CQ0.
The completion queue can hold six instructions, but no more than four integer instructions.
The other two instructions can be condition code or branch instructions. Long latency
instructions may cause the completion queue to fill, stalling dispatch until the long latency
instruction vacates the completion queue. The following instructions may cause the
completion queue to fill:
• Integer divide instructions
• Instructions that affect or use resources external to the core (load/store instructions,
and especially load/store string multiple/instructions)
MPC850 Family User's Manual