Hard Reset - Freescale Semiconductor MPC850 User Manual

11.3.1 Hard Reset

When a hard reset event occurs, the MPC850 determines its initial mode of operation by
sampling the values present on the data bus (D[0–31]) or from an internal default constant
(D[0–31] = 0x00000000). If the RSTCONF signal is asserted at sampling time, the
configuration is sampled from the data bus. If the RSTCONF signal is negated the internal
default value is selected. While HRESET and RSTCONF are asserted, the MPC850 weakly
pulls the data bus low, and the desired configuration is selected by driving the appropriate
bits high as shown in Figure 11-4.
Figure 11-4 shows a typical data bus configuration input circuit.
Configuration
Word
MPC850
MPC860
NOTE: The value of the internal pulldown resistor is not specified or guaranteed.
Figure 11-4. Data Bus Configuration Input Circuit
The configuration of the MPC850 following the assertion of PORESET is shown in
Figure 11-5 through Figure 11-7 While the PORESET input signal is being asserted, the
core assumes the default reset configuration (0x0000_0000). When PORESET is negated
or the CLKOUT signal begins oscillation, the hardware configuration is sampled from the
data bus every nine clock cycles on the rising edge of CLKOUT. The setup time required
for the data bus is 15 cycles and the maximum rise time of HRESET should be less than six
clock cycles. Refer to Section 11.3.2, "Soft Reset," for more information.
Figure 11-5 shows a reset operation with a short PORESET signal assertion. Note that the
configuration of the MPC850 is determined from the signal levels driven on the D[0–31]
signals following the assertion of RSTCONF and the negation of HRESET.
MUX
Chapter 11. Reset
MPC850 Reset Configuration
DX (Data Line)
HRESET
RSTCONF