Memory Reservation - Freescale Semiconductor MPC850 User Manual

MPC850
Figure 13-25. Termination Signals Protocol Basic Connection
CLKOUT
A[6–31]
R/W
TSIZ[0–1]
TS
Data
TA, BI, TEA
Figure 13-26. Termination Signals Protocol Timing Diagram

13.4.9 Memory Reservation

The MPC850 memory reservation protocol supports multilevel bus structures. For each
local bus, reservations are handled by the local reservation logic. The protocol tries to
optimize reservation cancellation such that a PowerPC processor is notified of memory
External Bus
Termination Signals
(TA, TEA, BI)
Slave 2
Slave 1
Slave 1 Slave 1
allowed to negates
drive acknowledge
acknowledge signals
signals and
'turns off'
Chapter 13. External Bus Interface
Slave 1
Slave 2
Slave 2 Slave 2
allowed to negates
drive acknowledge
acknowledge signals
signals and
'turns off'
Bus Operations