Dsi Exception (0X00300); Isi Exception (0X00400); External Interrupt Exception (0X00500) - Freescale Semiconductor MPC850 User Manual

Exceptions
Table 6-5. Register Settings after a Machine Check Interrupt Exception (Continued)
Register
MSR IPNo change
ME0
LE Copied from the ILE setting of the interrupted process
Others0
DSISR Set when the load/store bus is used:
0–140
15–16Set to bits 29-30 of the instruction if X-form instruction and to 0b00 if D-form.
17 Set to bit 25 of the instruction if X-form instruction and to bit 5 if D-form.
18–21Set to bits 21-24 of the instruction if X-form instruction and to bits 1-4 if D-form.
22–31Set to bits 6-15 of the instruction.
DAR When the load/store bus is used, DAR holds the EA of the data access that caused the exception.

6.1.2.3 DSI Exception (0x00300)

DSI exceptions are never generated by the hardware. Software may branch to this location
as a result of either implementation specific DTLB error interrupt or implementation
specific STLB miss interrupt.

6.1.2.4 ISI Exception (0x00400)

ISI exceptions is never generated by the hardware. The software may branch to this location
as a result of an implementation-specific ITLB error interrupt.

6.1.2.5 External Interrupt Exception (0x00500)

In the MPC850 the external interrupt is generated by the on-chip interrupt controller. It is
software acknowledged and maskable by MSR[EE], which hardware clears automatically
to disable external interrupts when any exception is taken.
When an external interrupt is detected, program execution continues until all previous
instructions retire from the completion queue and the exception is assigned to the
instruction last entry in the completion queue (at point B in Table 6-19). However, the
following conditions must be met before the instruction at the end of the queue can retire.
• The instruction must be completed without exception
• The instruction must either be a mtspr, mtmsr, rfi, a memory reference, or a
memory- or cache-control instruction.
Instructions not fitting these criteria are discarded along with any execution results. After
the exception handler completes, execution resumes with the first instruction that was
discarded. If all the instructions in the completion queue were allowed to complete,
execution at the end of the exception handler resumes with the next instruction. External
exception latency depends on the time required to reference memory. The measurement is
equal to the time taken for one of the following three events, in addition to the interval from
B to E as shown in Table 6-19.
• Longest load/store multiple/string instruction used
Setting
MPC850 Family User's Manual