Scc Uart Transmit Buffer Descriptor (Txbd) - Freescale Semiconductor MPC850 User Manual

Mpc850 family integrated communications microprocessor
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Table 22-10. SCC UART RxBD Status and Control Field Descriptions (Continued)
Bits
Name
11
FR
Framing error. Set when a character with a framing error (a character without a stop bit) is received and
located in the last byte of this buffer. A new Rx buffer is used to receive subsequent data.
12
PR
Parity error. Set when a character with a parity error is received and located in the last byte of this buffer.
A new Rx buffer is used to receive subsequent data.
13
Reserved, should be cleared.
14
OV
Overrun. Set when a receiver overrun occurs during reception.
15
CD
Carrier detect lost. Set when the carrier detect signal is negated during reception.
Section 21.3, "SCC Buffer Descriptors (BDs)," describes the data length and buffer pointer
fields.

22.18 SCC UART Transmit Buffer Descriptor (TxBD)

The CPM uses BDs to confirm transmission and indicate error conditions so the core knows
that buffers have been serviced. Figure 22-9 shows the SCC UART TxBD.
0
1
R
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Figure 22-9. SCC UART Transmit Buffer Descriptor (TxBD)
Table 22-11 describes TxBD status and control fields.
Table 22-11. SCC UART TxBD Status and Control Field Descriptions
Bit
Name
R
0
Ready.
0 The buffer is not ready. This BD and buffer can be modified. The CPM automatically clears R after
the buffer is sent or an error occurs.
1 The user-prepared buffer is waiting to begin transmission or is being transmitted. Do not modify the
BD once R is set.
1
Reserved, should be cleared.
W
2
Wrap (last buffer descriptor in TxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CPM sends data using the BD pointed to by
TBASE. The number of TxBDs in this table is determined only by the W bit and space constraints of
the dual-port RAM.
I
3
Interrupt.
0 No interrupt is generated after this buffer is processed.
1 SCCE[TX] is set after this buffer is processed by the CPM, which can cause an interrupt.
2
3
4
5
W
I
CR
A
CM
Chapter 22. SCC UART Mode
SCC UART Transmit Buffer Descriptor (TxBD)
Description
6
7
8
9
10
P
NS
Data Length
Tx Buffer Pointer
Description
11
12
13
14
15
CT

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