I2C Controller Transfers - Freescale Semiconductor MPC850 User Manual

33.3 I C Controller Transfers
2
To initiate a transfer, the master I
request to an I 2 C slave. The first byte of the message consists of a 7-bit slave port address
and a R/W request bit. Note that because the R/W request follows the slave port address in
the I 2 C bus specification, the R/W request bit must be placed in the lsb (bit 7) unless
operating in reverse data mode; see Section 33.4.1, "I2C Mode Register (I2MOD)."
To write to a slave, the master sends a write request (R/W = 0) along with either the target
slave's address or the general call (broadcast) address of all zeros, followed by the data to
be written. To read from a slave, the master sends a read request (R/W = 1) and the target
slave's address. When the target slave acknowledges the read request, the transfer direction
is reversed, and the master receives the slave's transmit buffers. If the receiver (master or
slave) does not acknowledge each byte transfer in the ninth bit frame, the transmitter signals
a transmission error event (I2ER[TXE]). An I
Figure 33-3.
SCL
SDA
Select master or slave mode for the controller using the I
(I2COM[M/S]). Set the master's start bit, I2COM[STR], to begin a transfer; setting a
slave's I2COM[STR] activates the slave to wait for a transfer request from a master.
If a master or slave transmitter's current TxBD[L] is set, transmission stops once the buffer
is sent; that is, I2COM[STR] must be set again to reactivate transfers. If TxBD[L] is zero,
once the current buffer is sent, the controller begins processing the next TxBD without
waiting for I2COM[STR] to be set again.
The following sections further detail the transfer process.
33.3.1 I C Master Write (Slave Read)
2
If the MPC850 is the master, prepare the transmit buffers and BDs before initiating a write.
Initialize the first transmit data byte with the slave address and write request (R/W = 0).
If the MPC850 is the slave target of the write, prepare receive buffers and BDs to await the
master's request. Figure 33-4 shows the timing for a master write.
2
C controller sends a message specifying a read or write
Start Condition
1 2 3 4 5 6
Data Byte
2
Figure 33-3. I C Transfer Timing
2
Chapter 33. I C Controller
2
C transfer timing diagram is shown in
Stop Condition
7 8 9
A
C
K
2
C command register

I2C Controller Transfers