Transfer Acknowledge And Data Sample Control (Uta, Dlt3) - Freescale Semiconductor MPC850 User Manual

User-Programmable Machines (UPMs)
Table 15-19. AMA/AMB Definition for DRAM Interface (Continued)
Data Bus
Memory Size
Width
32 bits 256 Kbyte
512 Kbyte
1 Mbyte
2 Mbyte
4 Mbyte
1 Mbyte
2 Mbyte
4 Mbyte
8 Mbyte
16 Mbyte
4 Mbyte
8 Mbyte
16 Mbyte
32 Mbyte
64 Mbyte
16 Mbyte
32 Mbyte
64 Mbyte
64 Mbyte
128 Mbyte
256 Mbyte
256 Mbyte

15.6.4.8 Transfer Acknowledge and Data Sample Control (UTA, DLT3)

During a memory access, the UTA bit of the RAM word controls the state of TA driven by
the UPM. TA is driven on the rising edge of GCLK2_50. Therefore, because TA is also
sampled on the rising edge of GCLK2_50, programming UTA to assert in the RAM word
causes the bus master to sample TA as asserted in the next cycle.
When a read access is handled by the UPM and the UTA bit is 0, the value of the DLT3 bit
in the same RAM word indicates when the data input is sampled by the internal bus master,
assuming that MxMR[GPLx4DIS] = 1.
• If G4T4/DLT3 functions as DLT3 and DLT3 = 1 in the RAM word, data is latched
on the falling edge of GCLK2_50 instead of the rising edge, which is normal. This
feature lets the user speed up the memory interface by latching data 1/2 clock early,
which can be useful during burst reads. This feature should be used only in systems
without external synchronous bus devices.
DRAM Address Pin Number
Row Column
8 8
9
10
11
12
9 9
10
11
12
13
10 10
11
12
13
14
11 11
12
13
12 12
13
14
13 13
MPC850 Family User's Manual
MPC850 Address
Pin Connection
A22–A29
A21–A29
A20–A29
A19–A29
A18–A29
A21–A29
A20–A29
A19–A29
A18–A29
A17–A29
A20–A29
A19–A29
A18–A29
A17–A29
A16–A29
A19–A29
A18–A29
A17–A29
A18–A29
A17–A29
A16–A29
A17–A29
AMx
000
001
010
011
100
101