Idma Requests For Memory/Memory Transfers; Idma Requests For Peripheral/Memory Transfers; Level-Sensitive Requests - Freescale Semiconductor MPC850 User Manual

IDMA Emulation

19.3.7.1 IDMA Requests for Memory/Memory Transfers

Because there is no internal mechanism, an externally-connected DREQ must still be used
to generate IDMA memory/memory transfer requests. This can be done using a
general-purpose I/O line or a general-purpose timer output.
To use a general-purpose I/O line, follow these steps:
1. Externally connect a general-purpose output line to DREQ.
2. Set RCCR[DRnM] (level-sensitive).
3. Drive the output low when the request generation should begin.
The IDMA controller continuously requests the bus until the current buffer chain is
completely transferred. The transfer terminates with an out-of-buffers error (IDSR[OB]).
To use a general-purpose timer output (TOUTx), follow these steps:
1. Externally connect a TOUTx to DREQ.
2. Clear RCCR[DRnM] (edge-sensitive).
3. Program the timer period to pace the IDMA requests (and thus bus utilization).
An interrupt handler can service the IDSR[DONE] interrupt and suspend the channel;
otherwise, the transfer terminates with an out-of-buffers error (IDSR[OB]).

19.3.7.2 IDMA Requests for Peripheral/Memory Transfers

Once an IDMA channel has been activated, an external peripheral requests a transfer using
DREQ. The user programs the RISC controller (the CP) configuration register (RCCR) to
make IDMA requests either edge- or level-sensitive. The RCCR settings also determine the
priority of DREQ relative to the SCCs. See Section 18.5.1, "RISC Controller Configuration
Register (RCCR)." Since DREQ0 and DREQ1 are multiplexed through PC15 and PC14
respectively, the port C pin assignment register and direction register must be configured as
well; see Section 34.4, "Port C."
Level-sensitive mode maximizes IDMA channel bandwidth for peripherals requiring high
transfer rates. For external peripherals that generate a pulsed transfer signal for each data
operand, edge-sensitive requests should be used.

19.3.7.2.1 Level-Sensitive Requests

Setting RCCR[DRnM] makes the corresponding IDMA channel level-sensitive to requests.
DREQ is sampled at rising edge of the clock. The peripheral requests service by asserting
DREQ and leaving it asserted as long as it needs service.
Each time the IDMA controller issues a bus cycle either to read or write the peripheral, it
asserts SDACK to acknowledge the original transfer request on DREQ. The IDMA channel
continues moving data in back-to-back DMA cycles until DREQ is negated. To ensure the
correct number of DMA transfers are performed, the peripheral must negate DREQ while
the IDMA is acknowledging the last data move, that is, while SDACK is asserted. DREQ
is sampled on the same rising edge on which TA is sampled to terminate the current cycle.
MPC850 Family User's Manual