Doze Low Mode - Freescale Semiconductor MPC850 User Manual

Power Control (Low-Power Modes)
Doze high mode
PLPRCR[LPM]=01. In doze high mode, the GCLKx frequency is determined by
SCCR[DFNH]. For more information about SCCR[DFNH], see Section 14.3.1.1, "The
Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2)." Note also that
PLPRCR[TMIST] should be cleared before entering doze high mode; for more
information, see Section 14.5.8, "TMIST: Facilitating Nesting of SIU Timer Interrupts."
The MPC850 leaves doze high mode and enter normal high mode when a pending interrupt
from the interrupt controller occurs. These interrupts include all internal and external
interrupt sources, if enabled. This action requires that SCCR[PRQEN] be set; otherwise,
the MPC850 will not wake up. When the MPC850 enters normal high mode,
PLPRCR[LPM] is cleared.
Upon resumption of processing in normal high or low mode, the MPC850 jumps to the
external interrupt vector to process the interrupt source. When the core returns from the
exception handler via rfi , it resumes processing from the instruction following that which
initiated entry into doze mode.The one exception to this is the decrementer, a wake-up
interrupt from the decrementer never causes a jump to the interrupt handler; instead
processing always resumes from the instruction following that which initiated entry into
low-power mode.

14.5.4 Doze Low Mode

Doze low mode is similar to Doze high mode, except that additionally the system clock
frequency has been reduced. In doze low mode, the GCLKx frequency is determined by
SCCR[DFNL]. For more information about SCCR[DFNL], see Section 14.3.1.1, "The
Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2)."
Doze low mode
PLPRCR[LPM]=01. Note also that PLPRCR[TMIST] should be cleared before entering
doze low mode; for more information, see Section 14.5.8, "TMIST: Facilitating Nesting of
SIU Timer Interrupts."
The MPC850 has the option to temporarily leave doze low mode and enter doze high mode
when CPM activity occurs. This option is enabled in SCCR[CRQEN]. When the CP
finishes servicing the peripheral request, the MPC850 automatically reenters doze low
mode.
The MPC850 leaves doze low mode and enter normal high mode when a pending interrupt
from the interrupt controller occurs. These interrupts include all internal and external
interrupt sources, if enabled. This action requires that SCCR[PRQEN] be set; otherwise,
the MPC850 will not wake up. When the MPC850enters normal high or normal low mode,
PLPRCR[LPM] is cleared.
When the MPC850 leaves doze low mode, it enters normal high mode if SCCR[PRQEN]
is set; otherwise it enters normal low mode.
is selected if
is selected if
MPC850 Family User's Manual
PLPRCR[CSRC]=0,
PLPRCR[CSRC]=1,
MSR[POW]=1, and
MSR[POW]=1, and