Programming The Idl Interface - Freescale Semiconductor MPC850 User Manual

The Time-Slot Assigner (TSA)
The MPC850 supports all channels of the IDL bus in the basic rate. Each bit in the IDL
frame can be routed to any SCC and SMC or they can assert a strobe output that supports
an external device.
The MPC850 supports the request-grant method for contention detection on the D channel
of the IDL basic rate and when the MPC850 has data to send on the D channel, it asserts
L1RQa. The physical layer device monitors the physical layer bus for activity on the D
channel and indicates that the channel is free by asserting L1GRa. The MPC850 samples
L1GRa when the IDL sync signal (L1RSYNCa) is asserted. If L1GRa is asserted, the
MPC850 sends the first zero of the opening flag in the first bit of the D channel. If a collision
is detected on the D channel, the physical layer device negates L1GRa. The MPC850 then
stops its transmission and resends the frame when L1GRa is reasserted. This procedure is
handled automatically for the first two buffers of a frame.
For the primary rate IDL, the MPC850 supports up to four 8-bit channels in the frame,
determined by the SI RAM programming. Additionally, the MPC850 can assert strobes to
support additional external IDL channels. The IDL interface supports the CCITT I.460
recommendation for data rate adaptation since it separately accesses each bit of the IDL
bus. The current-route RAM specifies the bits that are supported by the IDL interface and
the serial controller. The receiver accepts only the bits enabled by the Rx route RAM.
Likewise, the transmitter sends only the bits enabled in the Tx route RAM and three-states
L1TXDa.

20.2.5.2 Programming the IDL Interface

To program the IDL interface, first program SIMODE[GMa] to the IDL grant mode for that
channel. If the receive and transmit sections interface to the same IDL bus, set
SIMODE[CRTa] to internally connect the Rx clock and sync signals to the transmit section.
Then program the SI RAM used for the IDL channels to the preferred routing. See
Section 20.2.3.6, "SI RAM Programming Example."
Define the IDL frame structure by programming SIMODE[xFSD] to have a 1-bit delay
from frame sync to data, SIMODE[FE] to sample the sync on the falling edge, and
SIMODE[CE] to transmit on the rising edge of the clock. Program L1TXDa to be
three-stated when inactive via the parallel I/O open-drain register. To support the D channel,
set the appropriate SICR[GR] bit and program the RAM entry to route data to the chosen
SCC. The two definitions of IDL, 8- and 10-bit, are only supported by modifying the SI
RAM programming. In both cases, L1GRa is sampled with L1TSYNCa and transferred to
the D-channel SCC as a grant indication.
For example, based on the same 10-bit format as in Section 20.2.3.6, "SI RAM
Programming Example," implement an IDL bus using SCC2, SCC3, and SMC2 connected
to the TDM channel as follows:
Chapter 20. Serial Interface