Load And Store Instructions; Integer Load And Store Address Generation - Freescale Semiconductor MPC850 User Manual

of the rotated data is placed into the target register, and if the mask bit is 0 the associated
bit in the target register is unchanged), or ANDed with a mask before being placed into the
target register. The integer rotate instructions are listed in Table 5-5.
Rotate Left Word Immediate then AND with Mask
Rotate Left Word then AND with Mask
Rotate Left Word Immediate then Mask Insert
The integer shift instructions perform left and right shifts. Immediate-form logical
(unsigned) shift operations are obtained by specifying masks and shift values for certain
rotate instructions. Simplified mnemonics are provided to make coding of such shifts
simpler and easier to understand. The integer shift instructions are listed in Table 5-6.
Shift Left Word
Shift Right Word
Shift Right Algebraic Word Immediate
Shift Right Algebraic Word

5.2.4.2 Load and Store Instructions

Load and store instructions are issued and translated in program order; however, the
accesses can occur out of order. Synchronizing instructions are provided to enforce strict
ordering. This section describes the load and store instructions of the MPC850, which
consist of the following:
• Integer load instructions
• Integer store instructions
• Integer load and store with byte-reverse instructions
• Integer load and store multiple instructions
• Integer load and store string instructions

5.2.4.2.1 Integer Load and Store Address Generation

Integer load and store operations generate effective addresses using register indirect with
immediate index mode, register indirect with index mode, or register indirect mode. See
Section 5.2.2.2, "Effective Address Calculation," for information about calculating
effective addresses. Note that the MPC850 is optimized for load and store operations that
are aligned on natural boundaries, and operations that are not naturally aligned may suffer
performance degradation. Refer to Section 6.1.2.6.1, "Integer Alignment Exceptions," for
additional information about load and store address alignment exceptions.
Table 5-5. Integer Rotate Instructions
Name
Table 5-6. Integer Shift Instructions
Name
Chapter 5. MPC850 Instruction Set
Instruction Set Summary
Mnemonic
rlwinm (rlwinm.) rA,rS,SH,MB,ME
rlwnm (rlwnm.) rA,rS,rB,MB,ME
rlwimi (rlwimi.) rA,rS,SH,MB,ME
Mnemonic
slw (slw.) rA,rS,rB
srw (srw.) rA,rS,rB
srawi (srawi.) rA,rS,SH
sraw (sraw.) rA,rS,rB
Syntax
Syntax