Basic Structure Of The Core - Freescale Semiconductor MPC850 User Manual

The following is a list of the core's main features:
• 32-bit PowerPC architecture features
— User-level instruction set (not including floating-point instructions)
— Thirty-two, 32-bit general-purpose registers (GPRs)
— Registers required to support PowerPC user-level instruction set (except
floating-point instructions). These include the integer exception register (XER),
condition register (CR), link register (LR), and counter register (CTR).
— Time base upper and time base lower and registers (TBU and TBL)
— A subset of the supervisor-level registers for compliance with the following
PowerPC models:
– Configuration—Machine state register (MSR)
– Exception model—Save/restore registers 0 and 1 (SRR0 and SRR1), DSI
status register (DSISR), data address register (DAR)
— Core-specific registers compliant with PowerPC architecture
— Static branch prediction
— Precise exception model that includes the subset of the PowerPC exceptions that
supports the instruction set and memory management. The MPC850 implements
all PowerPC asynchronous exceptions (interrupts)—system reset, machine
check, decrementer, and external interrupts. MPC850-specific exceptions are
PowerPC-compliant.
— Separate 8-entry instruction and data translation lookaside buffers (TLBs)
• Core-specific features
— Fully static design
— Additional registers that support the MPC850-specific features
— The ability to optimally issue and retire one instruction per clock cycle
— Out-of-order execution and in-order completion
— Extensive debug/testing support

3.4 Basic Structure of the Core

The MPC850 core consists of the following subunits:
• Instruction unit (sequencer)—Consists of the branch processing unit (BPU), the
instruction queue, and the exception handling mechanism.
• Execution units—These consist of the following:
— Integer unit—Implements all integer arithmetic and logical instructions defined
by the PowerPC architecture:
— Load/store unit (LSU)—Implements all load and store instructions except
floating-point load/store instructions. Note that because the MPC850 does not
implement floating-point load and store instructions, this document refers to
integer load/store instructions simply as load/store instructions.
Chapter 3. The PowerPC Core
Basic Structure of the Core