I2C Registers - Freescale Semiconductor MPC850 User Manual

I2C Registers

An MPC850 I 2 C controller attempting a master read request could simultaneously be
targeted for an external master write (slave read). Both operations trigger the controller's
I2CER[RXB] event, but only one operation wins the bus arbitration. To determine which
operation caused the interrupt, software must verify that its transmit operation actually
completed before assuming that the received data is the result of its read operation.
Problems could also arise if the MPC850's I
and BD for a write request, but then is the target of a read request from another master.
Without software precautions, the I
transmit buffer originally intended for its own write request. To avoid this situation, a
higher-level handshake protocol must be used. For example, a master, before reading a
slave, writes the slave with a description of the requested data (which register should be
read, for example). This operation is typical with many I
33.4 I C Registers
2
The following sections describe the I
33.4.1 I C Mode Register (I2MOD)
2
2
The I C mode register, shown in Figure 33-6, controls the I
Bit 0
Field —
Reset
R/W
Addr
Table 33-1 describes I2MOD bit functions.
Bits Name
0–1 — Reserved and should be cleared.
2 REVD Reverse data. Determines the Rx and Tx character bit order.
0 Normal operation. The msb (bit 0) of each character is sent and received first.
1 Reverse data. The lsb (bit 7) of each character is sent and received first.
Note: Clearing REVD is strongly recommended to ensure consistent bit ordering across devices.
3 GCD General call disable. Determines whether the receiver acknowledges a general call address (all zeros).
0 General call address is enabled.
1 General call address is disabled.
4 FLT Clock filter. Determines if the I
0 SCL is not filtered.
1 SCL is filtered by a digital filter.
2 C controller responds to the other master with the
2
C registers.
1 2
REVD GCD
2
Figure 33-6. I C Mode Register (I2MOD)
Table 33-1. I2MOD Field Descriptions
2
C input clock SCL is filtered to prevent spikes in a noisy environment.
MPC850 Family User's Manual
2 C controller master sets up a transmit buffer
2 C devices.
2
C modes and clock source.
3 4
FLT
0000_0000
R/W
0x860
Description
5 6
PDIV EN
7