Cp Command Register (Cpcr) - Freescale Semiconductor MPC850 User Manual

CP Register Set and CP Commands
RMDS fields are described in Table 18-4.
Bits Name
0 ERAM4K Enable RAM microcode (at offset 4K)
0 Microcode may be executed only from the first 2 Kbytes of the dual-port RAM.
1 Microcode is also executed from the 2 Kbytes of the second half of the dual-port RAM with a
512-byte extension.
1–7 — Reserved, should be cleared.

18.5.3 CP Command Register (CPCR)

The PowerPC core can issue commands to control communications via the CP command
register (CPCR), shown in Figure 18-4. The CP commands handle special cases, such as
initializing or stopping a channel, and are protocol-dependent.
When the core issues a command it sets CPCR[FLG]. When the command completes, the
CP clears FLG to signal the core for the next command. The core must wait for FLG to be
cleared before issuing another CP command. The core can, however, issue the CP reset
command (CPCR = 0x8001) at any time, regardless of FLG.
Bit 0 1
Field RST
Reset
R/W
Addr
Table 18-5 describes CPCR fields.
Bits Name
0 RST CP reset command. Set by the core and cleared by the CP. Executing this command clears RST
and FLG within two general system clocks. The CPM reset routine takes approximately 60 clocks,
but CPM initialization can start immediately after this command is issued. Use RST to reset the
registers and parameters for all the channels (SCCs, USB, SMCs, SPI, and I
CPM and RISC timer table. RST does not, however, affect the serial interface or parallel I/O
registers.
0 No reset issued.
1 Reset issued.
1–3 — Reserved. Should be cleared.
4–7 OPCODE Operation code for the core-issued CP commands. See Table 18-7.
Table 18-4. RMDS Field Descriptions
2 3 4 5
— OPCODE
Figure 18-4. CP Command Register (CPCR)
Table 18-5. CPCR Field Descriptions
MPC850 Family User's Manual
Description
6 7 8 9 10
CH_NUM
0
R/W
0x9C0
Description
11 12 13 14
— FLG
2
C) as well as the
15