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These signals include the following:
• PORESET
• UPWAITA/GPL_A4/AS (if configured as AS or UPWAITA)
• KR/RETRY/IRQ4/SPKROUT (if configured as KR/RETRY or IRQ4)
• Any IRQx (if configured as IRQx)
• BR (if the MPC850's internal bus arbiter is used)
• BG (if an external bus arbiter is used)
12.4.2 JTAG and Debug Ports
Recommendations on configuration of the JTAG pins (including TMS, TRST, TDI, TDO,
and TCK) are made in Section 45.6, "Recommended TAP Configuration." See also
Section 11.4, "TRST and Power Mode Considerations."
TCK/DSCK or ALE_B/DSCK/AT1 (depending on the configuration of the DSCK
function) should be connected to ground through a pull-down resistor to disable Debug
Mode as a default. When required, a debug mode controller tool externally drives this signal
high actively to put the MPC850 into debug mode.
Note that TDI/DSDI should be pulled up to VCC to keep it from oscillating when unused.
12.4.3 Unused Inputs
In general, pull-up resistors should be used on any unused inputs to keep them from
oscillating. For example, if PCMCIA is not used, the PCMCIA input pins (WAIT_B,
IP_B[0–8]) should have external pull-up resistors. However, unused pins of port A, B, C,
or D can be configured as outputs, and, if they are configured as outputs they do not require
external terminations.
12.4.4 Unused Outputs
Unused outputs can be left unterminated.
12.5 Signal States during Hardware Reset
During hardware reset (HRESET or PORESET), the signals of the MPC850 behave as
follows:
• The bus signals are high-impedance.
• The port I/O signals are configured as inputs, and are therefore high-impedance.
• The memory controller signals are driven to their inactive state.
However, some signal functions are determined by the reset configuration. When HRESET
is asserted, these signals immediately begin functioning as determined by the reset
Chapter 12. External Signals
Signal States during Hardware Reset
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