Asynchronous Hdlc Frame Transmission Processing; Asynchronous Hdlc Frame Reception Processing - Freescale Semiconductor MPC850 User Manual

Asynchronous HDLC Frame Transmission Processing

25.2 Asynchronous HDLC Frame Transmission
Processing
The SCC in asynchronous HDLC mode (asynchronous HDLC controller) works with
minimal core intervention. When the core enables the transmitter and sets TxBD[R] in the
first BD of the table, the asynchronous HDLC controller fetches data from memory and
starts sending the frame. If the current TxBD[L] is set (last buffer of a frame), the CRC and
closing flag are appended. If TxBD[CM] is zero, the transmitter updates frame status bits
in the BD and clears TxBD[R]. If TxBD[I] is set, the controller sets SCCE[TXB] so an
interrupt can be generated after each buffer, after a group of buffers, or after each frame is
sent.
If TxBD[CM] is set, the asynchronous HDLC transmitter updates frame status bits in the
BD after transmission but does not clear TxBD[R]. The transmitter then proceeds to the
next TxBD and if necessary waits until it is ready. As the transmitter sends data, it performs
the transparency encoding specified by the protocol. See Section 25.4, "Transmitter
Transparency Encoding."
Figure 25-1. Asynchronous HDLC Frame Structure
BOF Address
8 bits 8 bits
To rearrange buffers, such as for error handling or to expedite data ahead of previously
linked buffers, issue a
directly changing the current TxBD pointer TBPTR. When the asynchronous HDLC
controller receives a
asynchronous HDLC abort sequence. It then sends idle characters until the
command is given, at which point it resumes transmission with the next TxBD.
TRANSMIT
25.3 Asynchronous HDLC Frame Reception
Processing
The asynchronous HDLC receiver is designed to work with minimal core intervention. It
can decode transparency characters, check the CRC of the frame, and detect errors on the
line and in the controller. When the core enables the receiver and the receiver detects a data
byte of the incoming frame preceded by one or more opening flags, the asynchronous
HDLC controller fetches the next BD. If RxBD[E] is set, the controller starts transferring
the incoming frame into the buffer. When the buffer is full, the controller clears RxBD[E].
If the incoming frame is larger than the buffer, the controller fetches the next BD, and if E
is set, continues transferring the rest of the frame into its buffer.
The receiver decodes the transparency character required by asynchronous HDLC protocol
as described in Section 25.5, "Receiver Transparency Decoding." When the frame ends, the
controller checks the incoming CRC field and writes it to the buffer. The controller then
Control
8 bits
command before modifying the TxBD table or
STOP TRANSMIT
command, it stops the transmission and sends the
STOP TRANSMIT
MPC850 Family User's Manual
Information
M * 8 bits
FCS (CRC) EOF
2 • 8 bits 8 bits
RESTART