Features - Freescale Semiconductor MPC850 User Manual

Chapter 18
Communications Processor
Transacting with the communications peripherals on a separate bus from the PowerPC core,
the CPM's 32-bit communications processor (CP) handles the low-level communications
tasks, freeing the core for higher-level tasks. The CP implements the chosen protocols using
the serial controllers and parallel interface port and manages the data transfer through the
serial DMA (SDMA) channels between the I/O channels and memory. It also manages
IDMA (independent DMA) channels and contains an internal timer used to implement
additional software timers.
The CP's architecture and instruction set are optimized for data communications and
processing required by many wire-line and wireless communications standards.

18.1 Features

The following lists the CP's main features:
• Performs lower-layer protocol processing for communication channels
• Protocol-processing microcode routines located in internal ROM
• Optional Motorola-supplied microcode packages run from dual-port RAM (The
microcode packages allow the addition of protocols and other enhancements.)
• Supports general-purpose DMA using two IDMA channels
• Supports DMA bursting for memory-to-memory IDMA
• Performs DMA of serial data to external memory.
• RISC timer table supports a maximum of 16 software timers
Chapter 18. Communications Processor