Disabling The Spll; Clock Signals - Freescale Semiconductor MPC850 User Manual

Clock Signals

• VDDSYN—The power supply pin for the analog SPLL circuitry. For requirements
concerning this power supply, refer to Section 14.4.3, "Clock Synthesizer Power
(VDDSYN, VSSSYN, VSSYN1).
• VSSSYN and VSSSYN1—Ground reference pins for the analog SPLL circuitry. For
requirements concerning this ground reference, refer to Section 14.4.3, "Clock
Synthesizer Power (VDDSYN, VSSSYN, VSSYN1).
• XFC—The external filter capacitor pin that connects to the off-chip capacitor for the
SPLL filter. One terminal of the capacitor is connected to XFC while the other
terminal is connected to the VDDSYN pin.
— For proper SPLL operation, the XFC capacitor must be low leakage, with a
minimum parallel parasitic resistance value of 30MΩ.
— The value of the XFC capacitor is based on the value of the MF field in the
PLPRCR. XFC should be selected so that it satisfies both the range of values
required by the MF determined at reset and by the MF value programmed as the
final operating value.
Table 14-2. XFC Capacitor Values Based on PLPRCR[MF]
MF Range
1 ≤ (MF+1) ≤ 4
MF > 4
— Note that the these ranges are not strict cutoffs; they merely represent ranges
where the best jitter performance will be achieved. If there is no overlap between
two ranges of operation, choose the minimum or maximum value of the
recommended XFC range for the normal operating frequency of the system,
whichever is nearest the range for the other frequency.

14.2.2.4 Disabling the SPLL

For special purposes, such as testing, it is possible to disable the SPLL. The SPLL is
disabled if VDDSYN is grounded. In this case, VCOOUT will be equal to OSCCLK/2.
Note that because the skew elimination provided by the SPLL is also disabled, this mode
of operation invalidates the timing of the MPC850. Thus, this mode must not be used as a
normal operating mode; its only valid use is for low-frequency testing of board integrity
during production.
14.3 Clock Signals
The MPC850 uses the following clocks, summarized in Table 14-3. These clocks are
described in the following three sections, grouped by their different sources.
Minimum Capacitance
XFC = [(MF+1) x 425] - 125
XFC = (MF+1) x 520
MPC850 Family User's Manual
Maximum Capacitance
XFC = [(MF+1) x 590] - 175
XFC = (MF+1) x 920
Unit
pF
pF