Hdlc Event Register (Scce)/Hdlc Mask Register (Sccm) - Freescale Semiconductor MPC850 User Manual

Table 23-9. SCCE/SCCM Field Descriptions (Continued)
Bits Name
14 TXB Transmit buffer. Enabled by setting TxBD[I]. TXB is set when a buffer is sent on the HDLC channel. For
the last buffer in the frame, TXB is not set before the last bit of the closing flag begins its transmission;
otherwise, it is set after the last byte of the buffer is written to the Tx FIFO.
15 RXB Receive buffer. Enabled by setting RxBD[I]. RXB is set when the HDLC channel receives a buffer that
is not the last in a frame.
Figure 23-8 shows interrupts that can be generated using the HDLC protocol.
Frame
Received by HDLC
Time
RXD Line Idle
CD
HDLC SCCE
CD
Events
NOTES
:
1. RXB event assumes receive buffers are 6 bytes each.
2. The second IDL event occurs after 15 ones are received in a row.
3. The FLG interrupts show the beginning and end of flag reception.
4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.
5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.
6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte
Frame
Transmitted by HDLC
TXD
RTS
CTS
HDLC SCCE
Events
NOTES:
1. TXB event shown assumes all three bytes were put into a single buffer.
2. Example shows one additional opening flag. This is programmable.
3. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.
Figure 23-8. SCC HDLC Interrupt Event Example

HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)

Stored in Rx Buffer
F F A A C I
IDL FLG FLG
Stored in Tx Buffer
Line Idle F F
CTS
Chapter 23. SCC HDLC Mode
Description
I I CR CR F
RXB RXF FLG
FLG
A A C CR CR F
TXB
Line Idle
IDL CD
Line Idle
CTS