Register Descriptions; Base Registers (Brx) - Freescale Semiconductor MPC850 User Manual

15.4 Register Descriptions

The following sections describe the registers used by the memory controller.

15.4.1 Base Registers (BRx)

The base registers (BR0–BR7) contain the base address and address types that the memory
controller uses to compare the value on the address bus with the current address accessed.
It also includes a memory attribute and selects the machine for memory operation handling.
Figure 15-5 shows the BRx register.
Bit 0 1
Field
Reset
R/W
Addr (IMMR & FFFF0000) + 0x100 (BR0), 0x0x108 (BR1), 0x110, (BR2), 0x118 (BR3), 0x120 (BR4), 0x128
Bit 16 17
Field BA
Reset
R/W
Addr (IMMR & FFFF0000) + 0x102 (BR0), 0x10A (BR1), 0x112, (BR2), 0x11A (BR3), 0x122 (BR4), 0x12A
After reset, BR0 has different default values than other BRx registers until the first write to
OR0.
Bit 0 1
Field
Reset
R/W
Addr
Bit 16 17
Field BA
Reset 0
R/W
Addr
*
The reset value of PS depends on the boot port size (BPS) field of the hard reset configuration word.
**
The reset value of V depends on the boot disable (BDIS) field of the hard reset configuration word.
2 3 4 5
(BR5), 0x130 (BR6), 0x138 (BR7)
18 19 20 21
AT PS PARE
(BR5), 0x132 (BR6), 0x13A (BR7)
Figure 15-5. Base Registers (BRx)
2 3 4 5
(IMMR & FFFF0000) + 0x100
18 19 20 21
AT PS PARE
000 *
(IMMR & FFFF0000) + 0x102
Figure 15-6. BR0 Reset Defaults
Chapter 15. Memory Controller
6 7 8 9
BA
0000_0000_0000_0000
R/W
22 23 24 25
WP MS
0000_0000_0000_0000
R/W
6 7 8 9
BA
0000_0000_0000_0000
R/W
22 23 24 25
WP MS
0 0 00
R/W
Register Descriptions
10 11 12 13 14
26 27 28 29 30
—
10 11 12 13 14
26 27 28 29 30
—
00_000
15
31
V
15
31
V
**