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7.3.2.2.3 Data Cache Unlock Cache Block Command
The unlock cache block command (DC_CST[CMD] = 0b1000) is used to unlock
previously locked cache blocks. To unlock a cache block:
1. Write the address of the cache block to be unlocked to the DC_ADR register.
2. Write the unlock cache block command (DC_CST[CMD] = 0b1000) to the
DC_CST register.
If the block is found in the cache (hit), it is unlocked and thereafter operates as a regular
valid cache block. If the block is not found in the cache (miss), no operation is performed.
There are no error cases for the unlock block command.
The data cache performs the unlock cache block command in one clock cycle.
7.3.2.2.4 Data Cache Unlock All Command
The data cache unlock all command (DC_CST[CMD] = 0b1010) is used to unlock the
entire data cache with a single command. When the unlock all command is performed, if a
cache block is locked, it is unlocked and thereafter operates as a regular valid cache block.
If a block is not locked or if it is marked invalid, no operation is performed. There are no
error cases for the unlock all command.
The data cache performs the unlock all command in one clock cycle.
7.3.2.2.5 Data Cache Invalidate All Command
The data cache invalidate all command (DC_CST[CMD] = 0b1100) causes all unlocked,
valid blocks in the data cache to be marked invalid, regardless of whether the data is
modified. Therefore, this command may effectively destroy modified data. To invalidate the
entire data cache the invalidate all command should be preceded by an unlock all command.
Note that the data cache is not automatically invalidated at hard reset.
As a result of the invalidate all command, the LRU bits of all cache blocks point to either
the unlocked way or to way 0 if both ways are unlocked. There are no error cases for the
invalidate all command.
The data cache performs the invalidate all command in one clock cycle.
7.3.2.2.6 Data Cache Flush Cache Block Command
The data cache flush cache block command (DC_CST[CMD] = 0b1110) is used to write
the contents of an unlocked, modified-valid cache block to memory and subsequently
invalidate that cache block. If the cache block is unmodified-valid, the cache block is
invalidated without writing the contents to memory. If the cache block is locked or if it is
marked invalid, no operation is performed.
If a bus error occurs while executing the DC_CST flush cache block command,
DC_CST[CCER1] is set and a machine check exception is generated. The data of the cache
block flagged by the bus error is contained in the copyback buffer; it will have already been
Chapter 7. Instruction and Data Caches
Cache Control Registers
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