Processor Version Register - Freescale Semiconductor MPC850 User Manual

MPC850 Register Implementation
Table 4-8. MSR Field Descriptions (Continued)
Bit(s) Name
1
22 BE Branch trace enable (Optional)
0 The processor executes branch instructions normally.
1 The processor generates a branch trace exception after completing the execution of a branch
instruction, regardless of whether the branch was taken.
Note: If the function is not implemented, this bit is treated as reserved.
23–24 — Reserved
25 IP Exception prefix. The setting of IP specifies whether an exception vector offset is prepended with Fs
or 0s. In the following description, nnnnn is the offset of the exception vector. See Table 6-1..
0 Exceptions are vectored to the physical address 0x000n_nnnn
1 Exceptions are vectored to the physical address 0xFFFn_nnnn
The reset value of IP is determined by the IIP bit (bit 2) in the hard reset configuration word. See
Section 11.3.1.1, "Hard Reset Configuration Word." Subsequent soft resets cause IP to revert to the
value latched during hard reset configuration.
1
26 IR Instruction address translation
0 Instruction address translation is disabled.
1 Instruction address translation is enabled.
For more information, see Chapter 8, "Memory Management Unit."
1
27 DR Data address translation
0 Data address translation is disabled.
1 Data address translation is enabled.
For more information, see Chapter 8, "Memory Management Unit."
28–29 — Reserved
1
30 RI Recoverable exception (for system reset and machine check exceptions).
0 Exception is not recoverable.
1 Exception is recoverable.
For more information, see Chapter 6, "Exceptions."
1
31 L E Little-endian mode enable
0 The processor runs in big-endian mode.
1 The processor runs in little-endian mode.
1
These bits are loaded into SRR1 when an exception is taken. These bits are written back into the MSR when an
rfi is executed.

4.1.2.3.2 Processor Version Register

The value of the PVR register's version field is 0x0050. The value of the revision field is
incremented each time the core is revised.
4.1.3 MPC850-Specific SPRs
Table 4-2 and Table 4-9 list SPRs specific to the MPC850. Debug registers, which have
additional protection, are described in Chapter 44, "System Development and Debugging."
Description
MPC850 Family User's Manual