Siu Interrupt Processing; Nonmaskable Interrupts—Irq0 And Swt - Freescale Semiconductor MPC850 User Manual

System Configuration

10.5.3 SIU Interrupt Processing

Figure 10-8 shows the general flow of SIU interrupt processing.
Assert external interrupt
10.5.3.1 Nonmaskable Interrupts—IRQ0 and SWT
Figure 10-9 is a logical representation of IRQ0.
SIEL[ED0]
IRQ0
Table 10-8 describes the differences between IRQ0 and other IRQ interrupts.
SIU interrupt occurs
Set bit in SIPEND
Bit set in SIMASK
to core
Figure 10-8. SIU Interrupt Processing
MUX
Level
FF
Edge
R
SIPEND[IRQ0] = 1
Figure 10-9. IRQ0 Logical Representation
MPC850 Family User's Manual
Start
Bit not set in SIMASK
SIEL[ED0]
MUX
Level
Q Edge
Q
End
NMI
SIPEND[IRQ0]