Smc Uart Event Register (Smce)/Mask Register (Smcm) - Freescale Semiconductor MPC850 User Manual

SMC in UART Mode
8-bit data, 1 start, and 1 stop, initialize the data length field to 3. To send three UART
characters of 9-bit data, 1 start, and 1 stop, the data length field should 6, because the three
9-bit data fields occupy three half words in memory (the 9 LSBs of each half word).
Tx buffer pointer points to the first location of the buffer. It can be even or odd, unless the
number of data bits in the UART character is greater than 8 bits, in which case the buffer
pointer must be even. For instance, the pointer to 8-bit data, 1 start, and 1 stop characters
can be even or odd, but the pointer to 9-bit data, 1 start, and 1 stop characters must be even.
The buffer can reside in internal or external memory.
30.3.12 SMC UART Event Register (SMCE)/Mask Register
(SMCM)
The SMC event register (SMCE) generates interrupts and report events recognized by the
SMC UART channel. When an event is recognized, the SMC UART controller sets the
corresponding SMCE bit. SMCE bits are cleared by writing ones; writing zeros has no
effect. The SMC mask register (SMCM) has the same bit format as SMCE. Setting an
SMCM bit enables, and clearing it disables, the corresponding interrupt. All unmasked bits
must be cleared before the CP clears the internal interrupt request.
Bit 0
Field —
Reset
R/W
Address
Figure 30-9. SMC UART Event Register (SMCE)/Mask Register (SMCM)
Table 30-10 describes SMCE/SMCM fields.
Bits Name
0 — Reserved, should be cleared.
1 BRKE Break end. Set no sooner than after one idle bit is received after the break sequence.
2 — Reserved, should be cleared.
3 BRK Break character received. Set when a break character is received. If a very long break sequence
occurs, this interrupt occurs only once after the first all-zeros character is received.
4 — Reserved, should be cleared.
5 BSY Busy condition. Set when a character is received and discarded due to a lack of buffers. Set no
sooner than the middle of the last stop bit of the first receive character for which there is no available
buffer. Reception resumes when an empty buffer is provided.
6 TX Tx buffer. Set when the transmit data of the last character in the buffer is written to the transmit FIFO.
Wait two character times to ensure that data is completely sent over the transmit pin.
7 RX Rx buffer. Set when a buffer is received and its associated RxBD is closed. Set no sooner than the
middle of the last stop bit of the last character that is written to the receive buffer.
1 2
BRKE —
0xA86 (SMCE1), 0xA96 (SMCE2)/ 0xA8A (SMCM1), 0xA9A (SMCM2)
Table 30-10. SMCE/SMCM Field Descriptions
MPC850 Family User's Manual
3 4
BRK —
0
R/W
Description
5 6
BSY TX
7
RX