Powerpc Architecture Compliance - Freescale Semiconductor MPC850 User Manual

PowerPC Architecture Compliance

• Supports 16 access protection groups (group protection overrides page protection)
• Separate 8-entry, fully-associative data translation lookaside buffer (DTLB) and
instruction TLB (ITLB) with the following features:
— Implementation-specific exceptions—ITLB and DTLB miss exceptions, ITLB
and DTLB error exceptions
— Supports PowerPC tlbie and tlbia instructions. The tlbsync instruction, which is
optional to PowerPC implementations, is not supported and is treated as a no-op
— Software tablewalk updates supported by DTLB and ITLB miss exceptions and
SPRs
— Each entry can be programmed to match user or supervisor accesses or both
— Two entries in each TLB can optionally be locked to ensure fast translation for
selected regions
• High performance
— 1 clock (zero wait state) access for a data cache hit and for an instruction cache
hit when the access is from the same page as the previous access
— 1 clock penalty for other TLB hit instruction accesses
• Low power consumption
8.2 PowerPC Architecture Compliance
The MPC850 core complies largely with the MMU as it is defined by the OEA, with the
following differences:
• The MPC850 does not implement the following PowerPC features:
— Block-address translation
— The optional direct-store functionality
— The memory coherency attribute
• The MPC850 supports the following additional features not defined by the PowerPC
architecture:
— Variable page sizes. The OEA defines 4-Kbyte pages only
— Programmable defaults for write-through and cache-inhibited memory attributes
when translation is disabled.
— Additional registers and exceptions for handling table walks in software.
Note that although the MPC850 does not define segment registers as they are defined by the
OEA, the concept of segment is retained as the memory space accessible to the level-one
table descriptors.
MPC850 Family User's Manual