Software Service Register (Swsr) - Freescale Semiconductor MPC850 User Manual

The Software Watchdog Timer
Although most software disciplines permit or encourage the watchdog concept, some
systems require a selection of timeout periods. For this reason, the software watchdog timer
provides a selectable range for the timeout period. Figure 10-16 shows the method for
handling this need. When a new value is loaded into SWTC, the software watchdog timer
is not updated until the servicing sequence is written to SWSR. If the SWE bit is loaded
with a zero, the modulus counter will not count.
SWE
Clock
Core
Disable
Clock
FRZ
Figure 10-16. Software Watchdog Timer Block Diagram

10.7.1 Software Service Register (SWSR)

The software service register (SWSR) is the location that the software watchdog timer
servicing sequence writes to. To prevent a SWT timeout, a write of 0x556C followed by
0xAA39 should be written to this register. The SWSR can be written at any time, but returns
all zeros when read.
Bit 0 1
Field
Reset
R/W
Addr
Figure 10-17. Software Service Register (SWSR)
Table 10-13 describes SWSR fields.
Bits Name
0–15 SEQ Sequence. This field is the pattern that is used to control the state of the software watchdog timer.
SWSR
Service
Logic
Divide
by 2,048
2 3 4 5
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x00E
Table 10-13. SWSR Field Descriptions
MPC850 Family User's Manual
Down-counter
Rollover = 0
MUX
SWP
6 7 8 9 10
SEQ
W
Description
SWTC
Reload
16-Bit
HRESET
or NMI
Timeout
11 12 13 14 15