Hdlc Event Register (Scce)/Hdlc Mask Register (Sccm) - Freescale Semiconductor MPC850 User Manual

HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)

23.11 HDLC Event Register (SCCE)/HDLC Mask
Register (SCCM)
The SCC event register (SCCE) is used as the HDLC event register to report events
recognized by the HDLC channel and to generate interrupts. When an event is recognized,
the SCC sets the corresponding SCCE bit. Interrupts generated through SCCE can be
masked in the SCC mask register (SCCM) which has the same bit format as the SCCE.
Setting an SCCM bit enables the corresponding interrupt; clearing a bit masks it. SCCE bits
are cleared by writing ones; writing zeros has no effect. All unmasked bits must be cleared
before the CPM clears the internal interrupt request. Figure 23-7 shows SCCE/SCCM for
HDLC operation.
Bit 0 1
Field —
Reset
R/W
Addr
Figure 23-7. HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
Table 23-9 describes SCCE/SCCM fields.
Bits Name
0–2 — Reserved, should be cleared.
3, 4 GLR/ Glitch on Rx/Tx. Set when the SCC detects a clock glitch on the receive/transmit clock. See
GLT Section 21.4.6, "Clock Glitch Detection."
5 DCC DPLL carrier sense changed. Set when the carrier sense status generated by the DPLL changes.
Real-time status can be read in SCCS[CS]. This is not the CD status reported in port C. Valid only
when the DPLL is used.
6 FLG Flag status. Set when the SCC stops or starts receiving HDLC flags. Real-time status can be read in
SCCS[FG].
7 IDL Idle sequence status changed. Set when HDLC line status changes. Real-time status of the line can
be read in SCCS[ID].
8 GRA Graceful stop complete. A
the transmitter has sent a frame in progress when the command was issued. Set immediately if no
frame was in progress when the command was issued.
9–10 — Reserved, should be cleared.
11 TXE Tx error. Indicates an error (CTS lost or underrun) has occurred on the transmitter channel.
12 RXF Rx frame. Set when the number of receive frames specified in RFTHR are received on the HDLC
channel. It is set no sooner than two clocks after the last bit of the closing flag is received. This event
is not maskable via the RxBD[I] bit.
13 BSY Busy condition. Indicates a frame arrived but was discarded due to a lack of buffers.
2 3 4 5
GLR GLT DCC FLG
0000_0000_0000_0000
0xA30 (SCCE2)/0xA34 (SCCM2); 0xA50 (SCCE3)/0xA54 (SCCM3)
Table 23-9. SCCE/SCCM Field Descriptions
GRACEFUL STOP TRANSMIT
MPC850 Family User's Manual
6 7 8 9
IDL GRA —
R/W
Description
command completed execution. Set as soon as
10 11 12 13
TXE RXF BSY TXB RXB
14 15