Overview - Freescale Semiconductor MPC850 User Manual

Mpc850 family integrated communications microprocessor
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Chapter 45
IEEE 1149.1 Test Access Port
The MPC850 provides a dedicated user-accessible test access port (TAP) that is fully
compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture. Problems associated with testing high-density circuit boards have led to
development of this standard under the sponsorship of the Test Technology Committee of
IEEE and the Joint Test Action Group (JTAG). The MPC850 implementation supports
circuit-board test strategies based on this standard.
The TAP consists of five dedicated signals, a 16-state TAP controller, and two test data
registers. A boundary scan register links all device signals into a single shift register. The
test logic, implemented using static logic design, operates independently of the device
system logic. The MPC850 TAP implementation provides the capability to:
• Perform boundary scan operations to check circuit-board electrical continuity.
• Bypass the MPC850 for a given circuit-board test by effectively reducing the
boundary scan register to a single cell.
• Sample the MPC850 system signals during operation and transparently shift out the
result in the boundary scan register.
• Disable the output drive to signals during circuit-board testing.

45.1 Overview

The MPC850 TAP implementation includes a TAP controller, a 4-bit instruction register,
and two test registers (a 1-bit bypass register and a 397-bit boundary scan register). The
TAP interface consists of the following signals:
• TCK—A test clock input to synchronize the test logic.
• TMS—A test mode select input (with an internal pull-up resistor) that is sampled on
the rising edge of TCK to sequence the TAP controller's state machine.
• TDI—A test data input (with an internal pull-up resistor) that is sampled on the
rising edge of TCK.
• TDO—A three-statable test data output that is actively driven in the shift-IR and
shift-DR controller states. TDO changes on the falling edge of TCK.
• TRST
An asynchronous reset with an internal pull-up resistor that provides
initialization of the TAP controller and other logic required by the standard.
Chapter 45. IEEE 1149.1 Test Access Port

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