Features - Freescale Semiconductor MPC850 User Manual

Chapter 14
Clocks and Power Control
The MPC850 clock system provides many different clocking options for all on-chip and
external devices. For its clock sources, the MPC850 contains phase-locked loop and crystal
oscillator support circuitry. The phase-locked loop circuitry can be used to provide a
high-frequency system clock from a low-frequency external source. Also, to enable flexible
power control, the MPC850 provides frequency dividers and a variety of low-power mode
options.
The MPC850 allows a system to optimize power utilization by providing performance
on-demand. This is implemented through a variety of programmable power-saving modes
with automatic wake-up features.
Figure 14-1 illustrates internal clock source and distribution that includes the system
phase-locked loop (SPLL), clock dividers, drivers, and crystal oscillator.

14.1 Features

The main features of the MPC850 clocks and power control system are as follows:
• Contains system PLL (SPLL)
• Supports crystal oscillator circuits
• Clock dividers are provided for low-power modes and internal clocks
• Contains five major power-saving modes
— Normal (high and low)
— Doze (high and low)
— Sleep
— Deep sleep
— Power down
Chapter 14. Clocks and Power Control