Sdma Registers - Freescale Semiconductor MPC850 User Manual

SDMA Registers

Once an SDMA channel obtains the external system bus, it remains master for the whole
transaction—a byte, half-word, word or burst transfer—before relinquishing the bus. This
feature, in combination with the zero-clock arbitration overhead provided by the U-bus,
increases bus efficiency and lowers latency.
To minimize the latency associated with slower, character-oriented protocols, an SDMA
writes each character to memory as it arrives without waiting for the next character, and
always reads using 16-bit half-word transfers. A transfer may take multiple bus cycles if the
memory provides a less than 32-bit port size. An SDMA uses back-to-back bus cycles for
the entire transfer—4-word bursts, 32-bit reads, and 8-, 16-, or 32-bit writes—before
relinquishing the bus. For example, an SDMA channel reading a 32-bit word from a 16-bit
memory takes two consecutive bus cycles.
An SDMA steals cycles with no arbitration overhead unless an external device is bus
master. Figure 19-2 shows an SDMA stealing a cycle from an internal bus master.
Other Cycle SDMA Cycle Other Cycle
CLK
TS
TA
SDMA Internally
Requests the Bus
Figure 19-2. SDMA U-Bus Arbitration (Cycle Steal)
19.2 SDMA Registers
All SDMA channels share one configuration register (SDCR), a status register (SDSR), a
mask register (SDMR), and a read-only, address register (SDAR). The configuration of
each serial controller also affects their dedicated SDMA channels' behavior. The following
sub-sections describe the SDMA registers.
19.2.1 SDMA Configuration Register (SDCR)
The SDMA configuration register (SDCR) configures all 14 virtual SDMA channels. It
controls the channels' U-bus priority level and freeze-signal (FRZ) behavior. It is always
read/write in supervisor mode, even though writing to the SDCR is not recommended
unless the CPM is disabled. Figure 19-3 shows the register format.
Chapter 19. SDMA Channels and IDMA Emulation