Bypass; Clamp; Hi–Z - Freescale Semiconductor MPC850 User Manual

of the associated output buffer. The SAMPLE/PRELOAD instruction also provides an
opportunity to obtain a snapshot of system data and control signals.
Note that there is no internal synchronization between the TCK and CLKOUT; the user
must provide some form of external synchronization between the JTAG operation at TCK
frequency and the system operation CLKOUT frequency to achieve meaningful results.

45.4.3 BYPASS

The BYPASS instruction creates a shift register path from TDI through the bypass register
to TDO, circumventing the 397-bit boundary scan register. This instruction is used to
enhance test efficiency when a component other than the MPC850 becomes the device
under test. The BYPASS instruction selects the single-bit bypass register as shown in
Figure 45-7.
SHIFT DR
FROM TDI
When the bypass register is selected by the current instruction, the shift register stage is set
to a logic zero on the rising edge of TCK in the capture-DR controller state. Therefore, the
first bit to be shifted out after selecting the bypass register is always a logic zero.

45.4.4 CLAMP

The CLAMP instruction selects the single-bit bypass register as shown in Figure 45-7
above, and the state of all signals driven from the system output pins is defined by the data
currently contained in the boundary scan register.
45.4.5 HI–Z
The HI-Z instruction is provided as a manufacturer's optional public instruction to avoid
back driving the output pins during circuit-board testing. When the HI-Z instruction is
invoked all output drivers, including the two-state drivers, are placed in a high impedance
state. The HI-Z instruction also selects the bypass register.
G1
0
1
MUX
1
Figure 45-7. Bypass Register
Chapter 45. IEEE 1149.1 Test Access Port
D
C
CLOCK DR
Instruction Register
TO TDO