Spi Event/Mask Registers (Spie/Spim); Spi Command Register (Spcom) - Freescale Semiconductor MPC850 User Manual

SPI Registers

31.4.2 SPI Event/Mask Registers (SPIE/SPIM)

The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI.
When an event is recognized, the SPI sets the corresponding SPIE bit. Clear SPIE bits by
writing a 1—writing 0 has no effect. Setting a bit in the SPI mask register (SPIM) enables
and clearing a bit masks the corresponding interrupt. Unmasked SPIE bits must be cleared
before the CPM clears internal interrupt requests. Figure 31-7 shows both registers.
Bit 0
Field —
Reset
R/W
Addr
Figure 31-7. SPI Event/Mask Registers (SPIE/SPIM)
Table 31-3 describes the SPIE/SPIM fields.
Bits Name
0–1 — Reserved, should be cleared.
2 MME Multimaster error. Set when SPISEL is asserted externally while the SPI is in master mode.
3 TXE Tx error. Set when an error occurs during transmission.
4 — Reserved, should be cleared.
5 BSY Busy. Set after the first character is received but discarded because no Rx buffer is available.
6 TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Wait two
character times to be sure data is completely sent over the transmit signal.
7 RXB Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed.

31.4.3 SPI Command Register (SPCOM)

The SPI command register (SPCOM), shown in Figure 31-8, is used to start SPI operation.
Bit 0
Field STR
Reset 0
R/W
Addr
1 2
MME
0xAA6 (SPIE); 0xAAA (SPIM)
Table 31-3. SPIE/SPIM Field Descriptions
1 2
Figure 31-8. SPI Command Register (SPCOM)
MPC850 Family User's Manual
3 4
TXE —
0
R/W
Description
3 4
—
0
R/W
0xAAD
5 6
BSY TXB
5 6
7
RXB
7