Bisync Mode Register (Psmr) - Freescale Semiconductor MPC850 User Manual

BISYNC Mode Register (PSMR)

Table 26-9 describes receive errors.
Error
Overrun The controller maintains a receiver FIFO for receiving data. The CP begins programming the SDMA
channel (if the buffer is in external memory) and updating the CRC when the first byte is received in
the Rx FIFO. If an Rx FIFO overrun occurs, the controller writes the received byte over the
previously received byte. The previous character and its status bits are lost. The channel then
closes the buffer, sets RxBD[OV], and generates the RXB interrupt if it is enabled. Finally, the
receiver enters hunt mode.
CD Lost during The channel stops receiving, closes the buffer, sets RxBD[CD], and generates the RXB interrupt if
Message not masked. This error has the highest priority. If the rest of the message is lost, no other errors are
Reception checked in the message. The receiver immediately enters hunt mode.
Parity The channel writes the received character to the buffer and sets RxBD[PR]. The channel stops
receiving, closes the buffer, sets RxBD[PR], and generates the RXB interrupt if it is enabled. The
channel also increments PAREC and the receiver immediately enters hunt mode.
CRC The channel updates the CR bit in the BD every time a character is received with a byte delay of
eight serial clocks between the status update and the CRC calculation. When control character
recognition is used to detect the end of the block and cause CRC checking, the channel closes the
buffer, sets the CR bit in the BD, and generates the RXB interrupt if it is enabled.
26.11 BISYNC Mode Register (PSMR)
The PSMR is used as the BISYNC mode register, shown in Figure 26-5. PSMR[RBCS,
RTR, RPM, TPM] can be modified on-the-fly.
Bit 0 1 2
Field NOS
Reset
R/W
Addr
Figure 26-5. Protocol-Specific Mode Register for BISYNC (PSMR)
Receive Errors
Table 26-9.
3 4 5 6
CRC RBCS RTR RVD DRT
0xA28 (PSMR2), 0xA48 (PSMR3)
MPC850 Family User's Manual
Description
7 8 9 10
—
0
R/W
11 12 13 14
RPM TPM
15