Immu Tablewalk Control Register (Mi_Twc) - Freescale Semiconductor MPC850 User Manual

Programming Model
Table 8-9 describes Mx_EPN fields.
Bits Name
0–19 EPN Effective page number for TLB entry. Default value is the EA of the last ITLB/DTLB miss
20–21 — Reserved. Ignored on write. Undefined on read
22 EV TLB entry valid bit.
0 TLB entry is invalid
1 TLB entry is valid. EV is set to 1 on each ITLB/DTLB miss.
23–27 — Reserved. Ignored on write. Returns 0 on read
28–31 ASID Address space ID of the ITLB/DTLB entry to be compared with M_CASID[CASID]. Loaded with
M_CASID on a TLB miss.

8.8.4 IMMU Tablewalk Control Register (MI_TWC)

The IMMU tablewalk control register (MI_TWC), shown in Figure 8-9, contains the access
protection group and page size of the entry to be loaded into the TLB.
Bit 0 1
Field
Reset
R/W
Bit 16 17 18
Field
Reset
R/W
SPR
Figure 8-9. IMMU Tablewalk Control Register (MI_TWC)
Table 8-10 describes MI_TWC fields.
Bits Name
0–22 — Reserved. Ignored on write. Returns 0 on read.
23–26 APG Access protection group. Up to 16 protection groups supported. Default for ITLB miss is 0
27 G Guarded memory attribute for entry
0 Nonguarded memory (default for ITLB miss)
1 Guarded memory
28–29 PS Page size level-one
00 Small (4 or 16 Kbyte. See MI_RPN[SPS]) Default for ITLB miss
01 512 Kbyte
10 Reserved
11 8 Mbyte
Table 8-9. Mx_EPN Field Descriptions
2 3 4 5
0000_0000_0000_0000
19 20 21
—
0
R/W
Table 8-10. MI_TWC Field Descriptions
MPC850 Family User's Manual
Description
6 7 8 9
—
R/W
22 23 24 25
APG
—
R/W
789
Description
10 11 12 13
26 27 28 29
G PS
— —
R/W R/W R/W
14 15
30 31
— V
0 —
R/W