Handling Errors In The Scc Uart Controller - Freescale Semiconductor MPC850 User Manual

Bit 0 1 2
Field —
Reset 0
R/W
Addr
Figure 22-5. Data Synchronization Register (DSR)
Table 22-6 describes DSR fields.
Bit Name
0 — 0b0
1–4 FSB Fractional stop bits. For 16× oversampling:
1111 Last transmitted stop bit 16/16. Default value after reset.
1110 Last transmitted stop bit 15/16.
...
1000 Last transmitted stop bit 9/16.
0xxx Invalid. Do not use.
For 32× oversampling:
1111 Last transmitted stop bit 32/32. Default value after reset.
1110 Last transmitted stop bit 31/32.
...
0000 Last transmitted stop bit 17/32.
For 8× oversampling:
1111 Last transmitted stop bit 8/8. Default value after reset.
1110 Last transmitted stop bit 7/8.
1101 Last transmitted stop bit 6/8.
1100 Last transmitted stop bit 5/8.
10xx Invalid. Do not use.
0xxx Invalid. Do not use.
The UART receiver can always receive fractional stop bits. The next character's start bit can begin
any time after the three middle samples have been taken.
5–6 — 0b11
7–8 — 0b00
9–14 — 0b111111
15 — 0b0

22.15 Handling Errors in the SCC UART Controller

The UART controller reports character reception and transmission error conditions via the
BDs, the error counters, and the SCCE. Modem interface lines can be monitored by the port
C pins. Transmission errors are described in Table 22-7.
3 4 5 6
FSB — —
1 1 1
0xA2E (DSR2), 0xA4E (DSR3)
Table 22-6. DSR Fields Descriptions
Chapter 22. SCC UART Mode
Handling Errors in the SCC UART Controller
7 8 9 10
— — — —
0 0 1 1
R/W
Description
11 12 13 14
— — — —
1 1 1 1
15
—
0