General-Purpose Signals (Gxtx, G0X) - Freescale Semiconductor MPC850 User Manual

15.6.4.4 General-Purpose Signals (GxTx, G0x)

The general-purpose signals (GPL[1–5]) have two bits in the RAM word that define the
logical value of the signal to be changed at the falling edge of GCLK1_50 or GCLK2_50.
GPL0 has two 2-bit fields that perform this function plus an additional function explained
below. GPL5 and GPL0 offer the following enhancements beyond the other GPLx signals:
• GPL5 can be controlled during phase 4 of the first clock cycle according to the value
of G5LS, as shown in Figure 15-42. This allows it to assert earlier (simultaneous
with TS, for an internal master), which can speed up the memory interface,
particularly when GPL5 is used as a control signal for external address multiplexers.
CLKOUT/
GCLK2_50
GCLK1_50
GPL5
TS
Value
Controlled
by G5LS
Clock Phase 4
• GPL0 can be controlled by an address line specified in MxMR[G0CLx]. To use this
feature, set G0H and G0L in the RAM word. For example, for a SIMM with multiple
banks, this address line can be used to switch between banks.
The state of GPL_x5 logic depends on the defined in Table 15-16. In the first clock cycle
of the slave access, GPL_x5 reflects the value of ORx[G5LS]; in subsequent cycles, its state
is determined by G5T4 and G5T3 in the RAM word. If the UPMB controls slave access,
ORx[G5LA] can be used to select the active GPL_x5 signal. G5LS applies only to memory
requests and not to RAM words executed by the
periodic timer requests.
Value Controlled by G5T4 and G5T3 on UPM
1 2 3
RAM Word 1
Figure 15-42. Early GPL5 Control
Chapter 15. Memory Controller
User-Programmable Machines (UPMs)
4 1 2
RAM Word 2
command, exception, or memory
RUN
3 4