Chip-Select And Write Enable Deassertion Timing - Freescale Semiconductor MPC850 User Manual

Figure 15-16. GPCM Peripheral Device Interface
Figure 15-17 shows CS as defined by the setup time required between the address lines and
CE. The user can configure ORx[ACS] to specify CS to meet this requirement.
Clock
Address
Figure 15-17. GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0)

15.5.1.2 Chip-Select and Write Enable Deassertion Timing

Figure 15-18 shows a basic connection between the MPC850 and a static memory device.
Here, CS is connected directly to CE of the memory device. The WE signals are connected
to the respective W signal in the memory device where each WE corresponds to a different
data byte.
MPC850
Address
CS
R/W
Data
TS
TA
ACS = 11
ACS = 10
CS
R/W
Data
Chapter 15. Memory Controller
General-Purpose Chip-Select Machine (GPCM)
Peripheral
Address
CE
R/W
Data