Exception Pattern Entry (Exen); Address Multiplexing (Amx) - Freescale Semiconductor MPC850 User Manual

Continued loop execution depends on the loop counter. If the counter is not zero, the next
RAM word executed is the loop start word. Otherwise, the next RAM word executed is the
one after the loop end word. Loops can be executed sequentially but cannot be nested.
Read single-beat cycle
Read burst cycle
Write single-beat cycle
Write burst cycle
Periodic timer expired

15.6.4.6 Exception Pattern Entry (EXEN)

When the MPC850 under UPM control begins accessing a memory device, the external
device may assert TEA, SRESET, or HRESET. An exception occurs when one of these
signals is asserted by an external device and the MPC850 begins closing the memory cycle
transfer. When one of these exceptions is recognized and EXEN in the RAM word is set,
the UPM branches to the special exception start address (EXS) and begins operating as the
pattern defined there specifies. See Table 15-15. The user should provide an exception
pattern to deassert signals controlled by the UPM in a controlled fashion. For DRAM
control, a handler should negate RAS and CAS to prevent data corruption. If EXEN = 0,
exceptions are deferred and execution continues. After the UPM branches to the exception
start address, it continues reading until the LAST bit is set in the RAM word.

15.6.4.7 Address Multiplexing (AMX)

To support many devices with multiplexed address signals, the upper address signals can
be driven on the lower address lines. MxMR[AMA] and MxMR[AMB] control which
upper address signals are on which lower address signals.
Note that this feature of internally multiplexing address signals should only be used in a
system where the MPC850 is the only external bus master. If other devices can be bus
masters, address multiplexing must be done in external logic. One of the UPM's output
signals can be used to control this external multiplexing logic; GPL5 has been specifically
enhanced for this. See the description of GPL5 in Section 15.6.4.4, "General-Purpose
Signals (GxTx, G0x)."
ORx[SAM] and the AMX field of the RAM words determine when the multiplexing occurs.
ORx[SAM] controls address multiplexing for the first clock cycle. The AMX field in the
RAM word determines the multiplexing for subsequent clock cycles. As an address is
driven off of the falling edge of GCLK1–50, the address in a particular clock cycle is
actually controlled by the previous RAM word, as shown in Figure 15-43.
Table 15-17. MxMR Loop Field Usage
Request Serviced
Chapter 15. Memory Controller
User-Programmable Machines (UPMs)
Loop Field
RLFx
RLFx
WLFx
WLFx
TLFx